Digital cameras and other imaging devices typically have an array of devices, such as pixels arranged on a CMOS microchip for capturing and storing images. Each device and its associated circuitry, the combination of which is often called the Active Pixel Sensor (APS), converts the light intensity detected at each pixel location of the image into a voltage signal that can be digitized for storage, reproduction, and manipulation.
FIG. 1 is a schematic diagram of showing one implementation of a conventional three-transistor APS 100 which digitizes one pixel of an image. The number of pixels in an APS 100 array determines the resolution of the captured image. A typical APS 100 pixel includes three transistors 120, 121, and 122, and a photodiode 125 disposed in a silicon area on top of which are disposed multiple metal layers. Multiple metal layers are typically required because the APS 100 requires five terminal traces for operation. This is because the width between each APS 100 on a conventional CMOS array only typically allows enough space for two terminal traces per metal layer. The five terminal traces include RESET 110, PRESET 111, Vdd 112, COLUMN 113, and ROW 114. Each APS 100 also includes a GROUND 115 terminal. By using a controller (not shown) to control the signals at each of the control terminals for the APS 100 in conjunction with all other contacts associated with other APSs 100 (not shown) in a CMOS array, light intensity striking the CMOS array, i.e., an image, may be detected and digitized.
FIG. 2 is a timing diagram of the conventional operation of the APS 100 of FIG. 1. The operation of the APS 100 includes a reset phase 200, an integration phase 220, and a readout phase 240. Each of these phases 200, 220, and 240 is described below with respect to the timing diagram.
Before an image is acquired, each APS 100 must first be “cleared” during the reset phase 200. This is to make sure that all the pixels in the CMOS array (not shown) have the same starting voltage when the photodiode 125 begins integrating light. During time period 201, the APS 100 is in a previous readout phase 240 and, thus (as is explained below with respect to the readout phase 240), the RESET 110 trace is set to a predetermined low voltage level (typically 0 volts) and the ROW 113 and PRESET 111 traces are set to a predetermined high voltage level (typically 2.5-5.0 volts). At t2, the RESET 110 trace is raised to a high voltage level so that the transistor 121 acts as a closed switch. As such, the voltage at node 130 is equal to the voltage at the PRESET 111 trace. The voltage at node 130 may turn on transistor 122, but any current that may flow through transistor 122 is inconsequential because any resultant signal on the COLUMN 113 trace will not be sensed until the readout phase 240 as described below. Next, the PRESET 111 trace is dropped to a predetermined low voltage level while the RESET 110 trace remains at the high voltage level. Thus, the voltage at node 130 becomes low which causes the parasitic capacitance (not shown) associated with the photodiode 125 to be discharged. Finally, the PRESET 111 trace is brought back to the high voltage level to charge the parasitic capacitance of the photodiode 125 to a predetermined starting voltage level to complete the reset phase 200.
Next, during the integration phase 220, after the photodiode 125 is reset, the RESET 110 trace is set to a low voltage so that the transistor 121 turns off at t3. Now, the photodiode 125 is ready for exposure to light from the image to be captured. During predetermined time period 204, the photodiode 125 is exposed to light. As is known, the photodiode 125 draws a reverse current that is proportional to the intensity of the light that is striking it, and thus, partially or fully discharges the parasitic capacitance.
After the predetermined integration time period 204, the readout phase 240 begins. The ROW 114 trace is brought to a high voltage level at t5 such that the transistor 120 becomes a closed switch and transistor 122 acts as a source follower. This results in the voltage at node 130, which represents the light intensity detected during the integration phase 220, biasing the voltage on the COLUMN 113 trace to this voltage level minus the VGS drop from the transistor 122. The COLUMN 113 trace is coupled to a constant current source (not shown) such that the voltage at node 130 will translate to a corresponding voltage on the COLUMN 113 trace via transistor 122. Since the voltage threshold of the transistor 122 is or is approximately the same for all transistors 122 in other APSs 100, the effects of the VGS drops cancel out such that processing circuitry (not shown) determines the intensity of the light at the pixel captured by the APS 100 based on the voltage on the COLUMN 113 trace.
Each phase described above is repeated for each row of APSs 100, i.e., pixels, in a CMOS array during an image capture procedure. Each row is cycled separately and typically done so in a rolling fashion. That is, when the first row transitions from the reset phase to the integration phase the next row begins the reset phase. Therefore, no row of pixels is ever being read while another row of pixels is being read.
One problem with the APSs 100 of FIG. 1 is that each APS 100 requires five terminal traces as described above. As a result, at least three layers of metal, in which the traces (here, two per layer) for each pixel are routed, are typically needed for the CMOS array. These layers of metal are typically disposed on top of the active silicon area in which the integration photodiodes diodes 125 and the transistors 120, 121, and 122 are formed. Furthermore, these metal layers are typically separated by relatively thick layers of dielectric for insulation. Consequently, a conventional CMOS array typically includes at least three layers of metal separated by dielectric.
FIG. 3 is a diagram of an area occupied by an APS 100 in a conventional CMOS array 300. The three layers 310, 311, and 312 of metal separated by oxide insulation 315 create a cavity 320 above each photodiode 125. These cavities 320 can cause two problems. First, the thicker and more numerous the metal and oxide layers, the more light is blocked from reaching the photodiodes 125 in the CMOS array 300. Therefore, as the thickness and number of the metal and oxide layers increases, the sensitivity of the CMOS array 300 decreases.
Second, the higher the cavities 320, the closer the angle of incidence 330 of the incoming light must be to the normal of the CMOS array 300 to reach the pixel as evidenced by the shaded region 325. Therefore, if the angle of incidence 330 is too great, then the photodiodes 125 may not capture the image properly. Furthermore, because of space constraints, a corrective optical train to reduce the angle of incidence may be impractical.
Consequently, it would be desirable to reduce the thickness and/or number of metal and oxide layers in a CMOS pixel array